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» Test pattern generation based on arithmetic operations
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104
Voted
DATE
2009
IEEE
106views Hardware» more  DATE 2009»
15 years 8 months ago
Generation of compact test sets with high defect coverage
Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide hi...
Xrysovalantis Kavousianos, Krishnendu Chakrabarty
ITC
1997
IEEE
129views Hardware» more  ITC 1997»
15 years 6 months ago
On Using Machine Learning for Logic BIST
This paper presents a new approach for designing test sequences to be generated on–chip. The proposed technique is based on machine learning, and provides a way to generate effi...
Christophe Fagot, Patrick Girard, Christian Landra...
83
Voted
ITC
1998
IEEE
73views Hardware» more  ITC 1998»
15 years 6 months ago
Maximization of power dissipation under random excitation for burn-in testing
This work proposes an approach to generate weighted random patterns which can maximally excite a circuit during its burn-in testing. The approach is based on a probability model a...
Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen
ECP
1999
Springer
138views Robotics» more  ECP 1999»
15 years 6 months ago
Numeric State Variables in Constraint-Based Planning
We extend a planning algorithm to cover simple forms of arithmetics. The operator preconditions can refer to the values of numeric variables and the operator postconditions can mod...
Jussi Rintanen, Hartmut Jungholt
PATMOS
2004
Springer
15 years 7 months ago
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic
The main result is the development, and delay comparison based on Logical Effort, of a number of high speed circuits for common arithmetic and related operations using threshold l...
Peter Celinski, Derek Abbott, Sorin Cotofana