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» Test pattern generation based on arithmetic operations
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IEEEAMS
2003
IEEE
15 years 7 months ago
Communication Pattern Based Node Selection for Shared Networks
Selection of the most suitable nodes on a network to execute a parallel application requires matching the network status to the application requirements. We propose and validate a...
Srikanth Goteti, Jaspal Subhlok
ASPDAC
2009
ACM
262views Hardware» more  ASPDAC 2009»
15 years 8 months ago
Fault modeling and testing of retention flip-flops in low power designs
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, ...
NIPS
1997
15 years 3 months ago
Learning Generative Models with the Up-Propagation Algorithm
Up-propagation is an algorithm for inverting and learning neural network generative models. Sensory input is processed by inverting a model that generates patterns from hidden var...
Jong-Hoon Oh, H. Sebastian Seung
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
15 years 8 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ITC
2002
IEEE
81views Hardware» more  ITC 2002»
15 years 6 months ago
Design Rewiring Using ATPG
—Logic optimization is the step of the very large scale integration (VLSI) design cycle where the designer performs modifications on a design to satisfy different constraints suc...
Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri