502 search results - page 8 / 101 » Test pattern generation based on arithmetic operations |
113
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ICCAD
2002
IEEE
15 years 10 months ago
2002
IEEE
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
124
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DSD
2007
IEEE
15 years 8 months ago
2007
IEEE
This paper discusses possibilities for a choice of a pseudorandom pattern generator that is to be used in combination with the column-matching based built-in self-test design meth...
DAC
2006
ACM
16 years 2 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
147
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CPM
1995
Springer
15 years 5 months ago
1995
Springer
We consider strings which are succinctly described. The description is in terms of straight-line programs in which the constants are symbols and the only operation is the concaten...
105
Voted
ICCAD
1995
IEEE
15 years 5 months ago
1995
IEEE
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...