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FPGA
2008
ACM
146views FPGA» more  FPGA 2008»
14 years 11 months ago
FPGA-optimised high-quality uniform random number generators
This paper introduces a method of constructing random number generators from four of the basic primitives provided by FPGAs: Flip-Flips, Lookup-Tables, Shift Registers, and RAMs. ...
David B. Thomas, Wayne Luk
MICRO
2000
IEEE
124views Hardware» more  MICRO 2000»
15 years 1 months ago
Calpa: a tool for automating selective dynamic compilation
Selective dynamic compilation systems, typically driven by annotations that identify run-time constants, can achieve significant program speedups. However, manually inserting ann...
Markus Mock, Craig Chambers, Susan J. Eggers
ISLPED
1995
ACM
96views Hardware» more  ISLPED 1995»
15 years 1 months ago
Towards a high-level power estimation capability
We will present a power estimation technique for digital integrated circuits that operates at the register transfer level RTL. Such a high-level power estimation capability is r...
Farid N. Najm
ICCAD
2008
IEEE
140views Hardware» more  ICCAD 2008»
15 years 6 months ago
Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
Huan Ren, Shantanu Dutt
JUCS
2010
143views more  JUCS 2010»
14 years 8 months ago
Design of Arbiters and Allocators Based on Multi-Terminal BDDs
: Assigning one (more) shared resource(s) to several requesters is a function of arbiters (allocators). This class of decision-making modules can be implemented in a number of ways...
Václav Dvorák, Petr Mikusek