624 search results - page 10 / 125 » Test set compaction algorithms for combinational circuits |
VLSID
2005
IEEE
15 years 9 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DATE
1999
IEEE
15 years 1 months ago
1999
IEEE
A novel approach to testing sequential circuits that uses multi-level decision diagram representations is introduced. The proposed algorithm consists of a combination of scanning ...
84
Voted
VTS
1998
IEEE
15 years 1 months ago
1998
IEEE
This paper presents a BIST architecture for Finite State Machines that exploits Cellular Automata (CA) as pattern generators and signature analyzers. The main advantage of the pro...
82
Voted
VTS
2003
IEEE
15 years 2 months ago
2003
IEEE
Irreversible computation necessarily results in energy dissipation due to information loss. While small in comparison to the power consumption of today’s VLSI circuits, if curre...
ASPDAC
2008
ACM
14 years 11 months ago
2008
ACM
Power dissipation is quickly becoming one of the most important limiters in nanometer IC design for leakage increases exponentially as the technology scaling down. However, power ...