624 search results - page 11 / 125 » Test set compaction algorithms for combinational circuits |
CC
2007
Springer
14 years 9 months ago
2007
Springer
Abstract. The problem of testing membership in the subset of the natural numbers produced at the output gate of a {∪, ∩,− , +, ×} combinational circuit is shown to capture a...
VTS
1997
IEEE
15 years 1 months ago
1997
IEEE
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking ex...
DATE
2000
IEEE
15 years 1 months ago
2000
IEEE
In this paper, an analysis of test time by CBET (which is an acronym for Combination of BIST and External Test) test approach is presented. The analysis validates that CBET test a...
DAC
2001
ACM
15 years 10 months ago
2001
ACM
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
ENGL
2007
14 years 9 months ago
2007
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...