624 search results - page 12 / 125 » Test set compaction algorithms for combinational circuits |
DFT
2002
IEEE
15 years 2 months ago
2002
IEEE
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
ITC
1989
IEEE
15 years 1 months ago
1989
IEEE
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
VLSID
2002
IEEE
15 years 10 months ago
2002
IEEE
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
67
Voted
ASIACRYPT
2001
Springer
15 years 2 months ago
2001
Springer
Compact and high-speed hardware architectures and logic optimization methods for the AES algorithm Rijndael are described. Encryption and decryption data paths are combined and all...
EUROGP
2004
Springer
15 years 2 months ago
2004
Springer
Abstract. In this paper we propose an approach to Genetic Programming based on code reuse and we test it in the design of combinational logic circuits at the gate-level. The circui...