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» Test set compaction algorithms for combinational circuits
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74
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DAC
2006
ACM
15 years 10 months ago
MARS-C: modeling and reduction of soft errors in combinational circuits
Due to the shrinking of feature size and reduction in supply voltages, nanoscale circuits have become more susceptible to radiation induced transient faults. In this paper, we pre...
Natasa Miskov-Zivanov, Diana Marculescu
VCIP
2003
147views Communications» more  VCIP 2003»
14 years 11 months ago
An objective method for combining multiple subjective data sets
International recommendations for subjective video quality assessment (e.g., ITU-R BT.500-11) include specifications for how to perform many different types of subjective tests. I...
Margaret H. Pinson, Stephen Wolf
IDEAL
2003
Springer
15 years 2 months ago
Improving the Efficiency of Frequent Pattern Mining by Compact Data Structure Design
Mining frequent patterns has been a topic of active research because it is computationally the most expensive step in association rule discovery. In this paper, we discuss the use ...
Raj P. Gopalan, Yudho Giri Sucahyo
90
Voted
EURODAC
1994
IEEE
130views VHDL» more  EURODAC 1994»
15 years 1 months ago
RESIST: a recursive test pattern generation algorithm for path delay faults
This paper presents Resist, a recursive test pattern generation (TPG) algorithm for path delay fault testing of scan-based circuits. In contrast to other approaches, it exploits t...
Karl Fuchs, Michael Pabst, Torsten Rössel
90
Voted
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
15 years 1 months ago
BiTeS: a BDD based test pattern generator for strong robust path delay faults
This paper presents an algorithm for generation of test patterns for strong robust path delay faults, i.e. tests that propagate the fault along a single path and additionally are ...
Rolf Drechsler