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» Test set compaction algorithms for combinational circuits
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BIBE
2007
IEEE
136views Bioinformatics» more  BIBE 2007»
15 years 1 months ago
A Two-Stage Gene Selection Algorithm by Combining ReliefF and mRMR
Abstract—Gene expression data usually contains a large number of genes, but a small number of samples. Feature selection for gene expression data aims at finding a set of genes ...
Yi Zhang, Chris H. Q. Ding, Tao Li
ICCAD
1997
IEEE
144views Hardware» more  ICCAD 1997»
15 years 3 months ago
Partial scan delay fault testing of asynchronous circuits
Asynchronous circuits operate correctly only under timing assumptions. Hence testing those circuits for delay faults is crucial. This paper describes a three-step method to detect...
Michael Kishinevsky, Alex Kondratyev, Luciano Lava...
MEMOCODE
2007
IEEE
15 years 6 months ago
Combining Multi-Valued Logics in SAT-based ATPG for Path Delay Faults
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
Stephan Eggersglüß, Görschwin Fey,...
GECCO
2003
Springer
148views Optimization» more  GECCO 2003»
15 years 4 months ago
Structural and Functional Sequence Test of Dynamic and State-Based Software with Evolutionary Algorithms
Evolutionary Testing (ET) has been shown to be very successful for testing real world applications [10]. The original ET approach focusesonsearching for a high coverage of the test...
André Baresel, Hartmut Pohlheim, Sadegh Sad...
ICES
2003
Springer
112views Hardware» more  ICES 2003»
15 years 4 months ago
Using Negative Correlation to Evolve Fault-Tolerant Circuits
In this paper, we show how artificial evolution can be used to improve the fault-tolerance of electronic circuits. We show that evolution is able to improve the fault tolerance of...
Thorsten Schnier, Xin Yao