624 search results - page 24 / 125 » Test set compaction algorithms for combinational circuits |
144
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EURODAC
1994
IEEE
15 years 8 months ago
1994
IEEE
This paper presents a multiple-FPGA-based experimentation board. The problem to be solved is that of implementing a circuit into a set of FPGAs. This board provides a hardware env...
133
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ICCAD
2006
IEEE
16 years 26 days ago
2006
IEEE
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
140
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ICCAD
2002
IEEE
16 years 25 days ago
2002
IEEE
A regular circuit structure called a Whirlpool PLA (WPLA) is proposed. It is suitable for the implementation of finite state machines as well as combinational logic. A WPLA is ...
116
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DAC
2002
ACM
16 years 4 months ago
2002
ACM
We propose a false-path-aware statistical timing analysis framework. In our framework, cell as well as interconnect delays are assumed to be correlated random variables. Our tool ...
137
Voted
DAC
2007
ACM
16 years 5 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...