624 search results - page 28 / 125 » Test set compaction algorithms for combinational circuits |
161
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TCAD
2008
15 years 4 months ago
2008
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
130
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ICCAD
1994
IEEE
15 years 8 months ago
1994
IEEE
We consider the problem of performance driven lookup-table (LUT) based technology mapping for FPGAs using a general delay model. In the general delay model, each interconnection e...
221
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POPL
2007
ACM
16 years 4 months ago
2007
ACM
Path profiles provide a more accurate characterization of a program's dynamic behavior than basic block or edge profiles, but are relatively more expensive to collect. This h...
181
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EVOW
1999
Springer
15 years 8 months ago
1999
Springer
A technique is proposed to reduce the peak power consumption of sequential circuits during test pattern application. High-speed computation intensive VLSI systems, as telecommunica...
142
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CVPR
2004
IEEE
16 years 6 months ago
2004
IEEE
For the past few years researches have been investigating enhancing tracking performance by combining several different tracking algorithms. We propose an analytically justified, ...