624 search results - page 31 / 125 » Test set compaction algorithms for combinational circuits |
117
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DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology al...
112
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized exces...
136
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DAC
1994
ACM
15 years 8 months ago
1994
ACM
A powerful combinational path sensitization engine is required for the efficient implementation of tools for test pattern generation, timing analysis, and delay fault testing. Path...
130
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ATS
2005
IEEE
15 years 9 months ago
2005
IEEE
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
133
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RTCSA
2005
IEEE
15 years 9 months ago
2005
IEEE
We propose a new architecture for a content protection system that conceals confidential data and algorithms in an FPGA as electrical circuits. This architecture is designed for a...