624 search results - page 33 / 125 » Test set compaction algorithms for combinational circuits |
116
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ASYNC
1999
IEEE
15 years 8 months ago
1999
IEEE
This paper discusses the application of the timing analysis tool ATACS to the high performance, self-resetting and delayed-reset domino circuits being designed at IBM's Austi...
125
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EURODAC
1995
IEEE
15 years 7 months ago
1995
IEEE
This paper presents a formal approach to test combinational circuits. For the sake of explanation we describe the basic algorithms with the help of the stuck–at fault model. Ple...
124
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AHS
2006
IEEE
15 years 10 months ago
2006
IEEE
Evolvable hardware refers to a self reconfigurable electronic circuit, where the circuit configuration is under the control of an evolutionary algorithm. Evolvable hardware has sh...
133
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VTS
2000
IEEE
15 years 8 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...
104
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ICCAD
1997
IEEE
15 years 8 months ago
1997
IEEE
A built-in self-test (BIST) methodology to test system backplanes by using BIST functionality in each of its constituent boards is presented. Since the configurations of systems ...