624 search results - page 36 / 125 » Test set compaction algorithms for combinational circuits |
129
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COCO
2009
Springer
15 years 10 months ago
2009
Springer
—We show that the rank of a depth-3 circuit (over any field) that is simple, minimal and zero is at most O(k3 log d). The previous best rank bound known was 2O(k2 ) (log d)k−2...
125
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ICCAD
2008
IEEE
16 years 29 days ago
2008
IEEE
We propose a post-placement physical synthesis algorithm that can apply multiple circuit synthesis and placement transforms on a placed circuit to improve the critical path delay ...
152
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AIPS
2006
15 years 5 months ago
2006
We present a new algorithm for conformant probabilistic planning, which for a given horizon produces a plan that maximizes the probability of success under quantified uncertainty ...
110
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DATE
2009
IEEE
15 years 10 months ago
2009
IEEE
A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are ...
147
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CEC
2009
IEEE
15 years 10 months ago
2009
IEEE
— In this paper, the performance assessment of the hybrid Archive-based Micro Genetic Algorithm (AMGA) on a set of bound-constrained synthetic test problems is reported. The hybr...