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» Test set compaction algorithms for combinational circuits
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DATE
2009
IEEE
127views Hardware» more  DATE 2009»
15 years 10 months ago
Sequential logic synthesis using symbolic bi-decomposition
This paper uses under-approximation of unreachable states of a design to derive incomplete specification of combinational logic. The resulting incompletely-specified functions are...
Victor N. Kravets, Alan Mishchenko
DAC
2004
ACM
15 years 7 months ago
Implicit pseudo boolean enumeration algorithms for input vector control
In a CMOS combinational logic circuit, the subthreshold leakage current in the standby state depends on the state of the inputs. In this paper we present a new approach to identif...
Kaviraj Chopra, Sarma B. K. Vrudhula
ISQED
2007
IEEE
148views Hardware» more  ISQED 2007»
15 years 10 months ago
On Accelerating Soft-Error Detection by Targeted Pattern Generation
Soft error due to ionizing radiation is emerging as a major concern for future technologies. The measurement unit for failures due to soft errors is called Failure-In-Time (FIT) t...
Alodeep Sanyal, Kunal P. Ganeshpure, Sandip Kundu
DAC
2004
ACM
15 years 7 months ago
On test generation for transition faults with minimized peak power dissipation
This paper presents a method of generating tests for transition faults using tests for stuck-at faults such that the peak power is the minimum possible using a given set of tests ...
Wei Li, Sudhakar M. Reddy, Irith Pomeranz
COR
2007
143views more  COR 2007»
15 years 4 months ago
A memetic algorithm for channel assignment in wireless FDMA systems
A new problem encoding is devised for the minimum span frequency assignment problem in wireless communications networks which is compact and general. Using the new encoding, which...
Sung-Soo Kim, Alice E. Smith, Jong-Hyun Lee