624 search results - page 38 / 125 » Test set compaction algorithms for combinational circuits |
128
click to vote
ATS
2000
IEEE
15 years 8 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
118
click to vote
ASPDAC
2004
ACM
15 years 7 months ago
2004
ACM
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
163
click to vote
CVPR
2011
IEEE
15 years 10 days ago
2011
IEEE
A convenient way of dealing with image sets is to represent them as points on Grassmannian manifolds. While several recent studies explored the applicability of discriminant analy...
155
Voted
EH
1999
IEEE
15 years 8 months ago
1999
IEEE
An evolutionary algorithm is used to evolve a digital circuit which computes a simple hash function mapping a 16bit address space into an 8-bit one. The target technology is FPGA,...
139
click to vote
ISVLSI
2003
IEEE
15 years 9 months ago
2003
IEEE
This paper describes a technique for re-ordering of scan cells to minimize power dissipation that is also capable of reducing the area overhead of the circuit compared to a random...