624 search results - page 39 / 125 » Test set compaction algorithms for combinational circuits |
119
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VTS
1999
IEEE
15 years 8 months ago
1999
IEEE
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
113
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DFT
2002
IEEE
15 years 9 months ago
2002
IEEE
1 The objective of this paper is to propose a new fault model suitable for test pattern generation for an FPGA configured to implement a given application. The paper demonstrates t...
162
Voted
GLVLSI
2010
IEEE
15 years 9 months ago
2010
IEEE
Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising directio...
133
Voted
VTS
1995
IEEE
15 years 7 months ago
1995
IEEE
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
125
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DAC
2004
ACM
16 years 5 months ago
2004
ACM
An important primitive in the hardware implementations of linear DSP transforms is a circuit that can multiply an input value by one of several different preset constants. We prop...