624 search results - page 45 / 125 » Test set compaction algorithms for combinational circuits |
126
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FLAIRS
2001
15 years 5 months ago
2001
Recently we have proposed an algorithm of constructing hierarchical neural network classifiers (HNNC), that is based on a modification of error back-propagation. This algorithm co...
144
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IROS
2007
IEEE
15 years 10 months ago
2007
IEEE
— We present a novel technique for the detection of hand-thrown objects in a video sequence. Our method runs in real-time and was designed to be used as a component in a deployed...
132
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VLSID
2002
IEEE
16 years 4 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
170
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TAICPART
2010
IEEE
15 years 2 months ago
2010
IEEE
Abstract. With pairwise testing, the test model is a list of N parameters. Each test case is an N-tuple; the test space is the cross product of the N parameters. A pairwise test is...
131
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DAC
2008
ACM
16 years 5 months ago
2008
ACM
An effective technique to save power during scan based test is to switch off unused scan chains. The results obtained with this method strongly depend on the mapping of scan flip-...