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» Test set compaction algorithms for combinational circuits
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ICML
2006
IEEE
16 years 5 months ago
Combined central and subspace clustering for computer vision applications
Central and subspace clustering methods are at the core of many segmentation problems in computer vision. However, both methods fail to give the correct segmentation in many pract...
Le Lu, René Vidal
ICCAD
1995
IEEE
163views Hardware» more  ICCAD 1995»
15 years 7 months ago
Signal integrity optimization on the pad assignment for high-speed VLSI design
Pad assignment with signal integrity optimization is very important for high-speed VLSI design. In this paper, an efficient method is proposed to effectively minimize both simulta...
Kai-Yuan Chao, D. F. Wong
IOLTS
2002
IEEE
148views Hardware» more  IOLTS 2002»
15 years 9 months ago
Active Replication: Towards a Truly SRAM-Based FPGA On-Line Concurrent Testing
The reusing of the same hardware resources to implement speed-critical algorithms, without interrupting system operation, is one of the main reasons for the increasing use of reco...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
CONSTRAINTS
2007
112views more  CONSTRAINTS 2007»
15 years 4 months ago
Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
Francisco Azevedo
136
Voted
FLAIRS
2006
15 years 5 months ago
Using Web Searches on Important Words to Create Background Sets for LSI Classification
The world wide web has a wealth of information that is related to almost any text classification task. This paper presents a method for mining the web to improve text classificati...
Sarah Zelikovitz, Marina Kogan