624 search results - page 6 / 125 » Test set compaction algorithms for combinational circuits |
VTS
2005
IEEE
15 years 3 months ago
2005
IEEE
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
DATE
1998
IEEE
15 years 1 months ago
1998
IEEE
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
FPGA
1997
ACM
15 years 1 months ago
1997
ACM
Programmable logic architectures increase in capacity before commercial circuits are designed for them, yielding a distinct problem for FPGA vendors: how to test and evaluate the ...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
— In this paper, we present a test generation framework for testing of quantum cellular automata (QCA) circuits. QCA is a nanotechnology that has attracted significant recent at...
VTS
2000
IEEE
15 years 1 months ago
2000
IEEE
We present a low-cost on-line test methodology for RTL controller-datapath pairs, based on the notion of path invariance. The fundamental observation supporting the proposed metho...