624 search results - page 89 / 125 » Test set compaction algorithms for combinational circuits |
149
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ICML
2007
IEEE
16 years 5 months ago
2007
IEEE
Given a sample covariance matrix, we examine the problem of maximizing the variance explained by a particular linear combination of the input variables while constraining the numb...
137
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JCO
2011
14 years 11 months ago
2011
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such th...
138
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DAC
2006
ACM
15 years 10 months ago
2006
ACM
Microfluidics-based biochips, also referred to as lab-on-a-chip (LoC), are devices that integrate fluid-handling functions such as sample preparation, analysis, separation, and de...
128
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SBCCI
2005
ACM
15 years 9 months ago
2005
ACM
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
155
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CVPR
2001
IEEE
16 years 6 months ago
2001
IEEE
This paper explores a view-based approach to recognize free-form objects in range images. We are using a set of local features that are easy to calculate and robust to partial occ...