624 search results - page 9 / 125 » Test set compaction algorithms for combinational circuits |
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Test sets for path delay faults in circuits with large numbers of paths are typically generated for path delay faults associated with the longest circuit paths. We show that such ...
74
Voted
ICCAD
1995
IEEE
15 years 1 months ago
1995
IEEE
Recently a deterministic built-in self-test scheme has been presented based on reseeding of multiple-polynomial linear feedback shift registers. This scheme encodes deterministic ...
DATE
2005
IEEE
15 years 3 months ago
2005
IEEE
We investigate a new fault ordering heuristic for test generation in full-scan circuits. The heuristic is referred to as the accidental detection index. It associates a value ADI ...
ATS
2009
IEEE
15 years 4 months ago
2009
IEEE
SAT-based automatic test pattern generation has several advantages compared to conventional structural procedures, yet often yields too large test sets. We present a dynamic compa...
69
Voted
DATE
2002
IEEE
15 years 2 months ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...