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TC
1998
15 years 5 days ago
Abstraction Techniques for Validation Coverage Analysis and Test Generation
ion Techniques for Validation Coverage Analysis and Test Generation Dinos Moundanos, Jacob A. Abraham, Fellow, IEEE, and Yatin V. Hoskote —The enormous state spaces which must be...
Dinos Moundanos, Jacob A. Abraham, Yatin Vasant Ho...
VLSID
2007
IEEE
154views VLSI» more  VLSID 2007»
16 years 28 days ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used i...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di...
BMCBI
2010
176views more  BMCBI 2010»
14 years 10 months ago
Haplotype association analyses in resources of mixed structure using Monte Carlo testing
Background: Genomewide association studies have resulted in a great many genomic regions that are likely to harbor disease genes. Thorough interrogation of these specific regions ...
Ryan Abo, Jathine Wong, Alun Thomas, Nicola J. Cam...
NOCS
2009
IEEE
15 years 7 months ago
A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network
This paper presents a many-core heterogeneous computational platform that employs a GALS compatible circuit-switched on-chip network. The platform targets streaming DSP and embedd...
Anh T. Tran, Dean Truong, Bevan M. Baas
103
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SLIP
2005
ACM
15 years 6 months ago
Multilevel full-chip routing with testability and yield enhancement
We propose in this paper a multilevel full-chip routing algorithm that improves testability and diagnosability, manufacturability, and signal integrity for yield enhancement. Two ...
Katherine Shu-Min Li, Chung-Len Lee, Yao-Wen Chang...