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ATS
2003
IEEE
98views Hardware» more  ATS 2003»
15 years 6 months ago
Automatic Design Validation Framework for HDL Descriptions via RTL ATPG
We present a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG generates the test ...
Liang Zhang, Michael S. Hsiao, Indradeep Ghosh
VTS
2002
IEEE
126views Hardware» more  VTS 2002»
15 years 5 months ago
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
135
Voted
RTAS
2006
IEEE
15 years 6 months ago
Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems
Operating systems for reconfigurable devices enable the development of embedded systems where software tasks, running on a CPU, can coexist with hardware tasks running on a recon...
Rodolfo Pellizzoni, Marco Caccamo
94
Voted
LCPC
2005
Springer
15 years 6 months ago
Interprocedural Symbolic Range Propagation for Optimizing Compilers
Abstract. We have designed and implemented an interprocedural algorithm to analyze symbolic value ranges that can be assumed by variables at any given point in a program. Our algor...
Hansang Bae, Rudolf Eigenmann
95
Voted
PROCEDIA
2010
113views more  PROCEDIA 2010»
14 years 11 months ago
Exploring utilisation of GPU for database applications
This study is devoted to exploring possible applications of GPU technology for acceleration of the database access. We use the n-gram based approximate text search engine as a tes...
Slawomir Walkowiak, Konrad Wawruch, Marita Nowotka...