244 search results - page 18 / 49 » Testing Digital Circuits with Constraints |
112
Voted
ICCAD
1996
IEEE
15 years 9 months ago
1996
IEEE
The functional validation of a state-of-the-art digital design is usually performed by simulation of a register-transfer-level model. The degree to which the testvector suite cove...
145
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ICCAD
2009
IEEE
15 years 2 months ago
2009
IEEE
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
162
Voted
MTDT
2003
IEEE
15 years 10 months ago
2003
IEEE
ct Defect-based testing for digital logic concentrates primarily on methods of test application, including for example at-speed structural tests and IDDQ testing. In contrast, defe...
155
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VTS
2007
IEEE
15 years 11 months ago
2007
IEEE
In this paper, a novel test point insertion methodology is presented for RTL designs that aims to reduce the data volume of scan-based transition delay tests. Test points are iden...
110
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DSD
2002
IEEE
15 years 10 months ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...