111 search results - page 4 / 23 » Testing Input Output Partial Order Automata |
163
click to vote
LICS
2012
IEEE
13 years 4 months ago
2012
IEEE
—Data trees are trees in which each node, besides carrying a label from a finite alphabet, also carries a data value infinite domain. They have been used as an abstraction mode...
103
Voted
FORTE
2000
15 years 3 months ago
2000
The paper addresses the problem of test derivation from partially defined specifications. A specification is modeled by an Input/Output FSM such that transitions from some states ...
111
Voted
LATA
2009
Springer
15 years 8 months ago
2009
Springer
We propose an algorithm that given as input a full word w of length n, and positive integers p and d, outputs (if any exists) a maximal p-periodic partial word contained in w with ...
112
click to vote
DDECS
2009
IEEE
15 years 8 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
76
Voted
TVLSI
1998
15 years 1 months ago
1998
Abstract—Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we ...