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DSD
2010
IEEE
171views Hardware» more  DSD 2010»
14 years 8 months ago
Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG
— In this paper we propose a new method of test patterns compression based on a design of a dedicated SAT-based ATPG (Automatic Test Pattern Generator). This compression method i...
Jiri Balcarek, Petr Fiser, Jan Schmidt
SERP
2007
14 years 11 months ago
From Functional Requirements through Test Evaluation Design to Automatic Test Data Patterns Retrieval - a Concept for Testing of
- Functional testing of software dedicated for hybrid embedded systems should start at the early development phase and requires analysis of discrete and continuous signals, where t...
Justyna Zander-Nowicka, Abel Marrero Pérez,...
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
15 years 9 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
ITC
2000
IEEE
101views Hardware» more  ITC 2000»
15 years 1 months ago
Reducing test data volume using external/LBIST hybrid test patterns
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...
Debaleena Das, Nur A. Touba