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101
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DDECS
2007
IEEE
127views Hardware» more  DDECS 2007»
15 years 9 months ago
Instance Generation for SAT-based ATPG
— Recently, there is a renewed interest in Automatic Test Pattern Generation (ATPG) based on Boolean Satisfiability (SAT). This results from the availability of very powerful SA...
Daniel Tille, Görschwin Fey, Rolf Drechsler
ISMVL
2007
IEEE
92views Hardware» more  ISMVL 2007»
15 years 8 months ago
Experimental Studies on SAT-Based ATPG for Gate Delay Faults
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
Stephan Eggersglüß, Daniel Tille, G&oum...
DAC
2000
ACM
15 years 7 months ago
Modeling and simulation of real defects using fuzzy logic
Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the trad...
Amir Attarha, Mehrdad Nourani, Caro Lucas
129
Voted
DAC
2002
ACM
16 years 3 months ago
Embedded software-based self-testing for SoC design
At-speed testing of high-speed circuits is becoming increasingly difficult with external testers due to the growing gap between design and tester performance, growing cost of high...
Angela Krstic, Wei-Cheng Lai, Kwang-Ting Cheng, Li...
113
Voted
EDBT
2008
ACM
160views Database» more  EDBT 2008»
15 years 4 months ago
Taxonomy-superimposed graph mining
New graph structures where node labels are members of hierarchically organized ontologies or taxonomies have become commonplace in different domains, e.g., life sciences. It is a ...
Ali Cakmak, Gultekin Özsoyoglu