Sciweavers

1610 search results - page 132 / 322
» Testing Patterns
Sort
View
119
Voted
ATS
2004
IEEE
87views Hardware» more  ATS 2004»
15 years 6 months ago
Low Power BIST with Smoother and Scan-Chain Reorder
In this paper, we propose a low-power testing methodology for the scan-based BIST. A smoother is included in the test pattern generator (TPG) to reduce average power consumption d...
Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu
106
Voted
AAAI
2008
15 years 5 months ago
Computing Observation Vectors for Max-Fault Min-Cardinality Diagnoses
Model-Based Diagnosis (MBD) typically focuses on diagnoses, minimal under some minimality criterion, e.g., the minimal-cardinality set of faulty components that explain an observa...
Alexander Feldman, Gregory M. Provan, Arjan J. C. ...
118
Voted
ET
2010
98views more  ET 2010»
15 years 1 months ago
MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
Stephan Eggersglüß, Görschwin Fey,...
138
Voted
EURODAC
1994
IEEE
145views VHDL» more  EURODAC 1994»
15 years 6 months ago
Testability analysis and improvement from VHDL behavioral specifications
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
Xinli Gu, Krzysztof Kuchcinski, Zebo Peng
121
Voted
CHI
2010
ACM
15 years 9 months ago
Understanding and evaluating cooperative games
Cooperative design has been an integral part of many games. With the success of games like Left4Dead, many game designers and producers are currently exploring the addition of coo...
Magy Seif El-Nasr, Bardia Aghabeigi, David Milam, ...