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102
Voted
DSD
2007
IEEE
83views Hardware» more  DSD 2007»
15 years 9 months ago
Hierarchical Identification of Untestable Faults in Sequential Circuits
Similar to sequential test pattern generation, the problem of identifying untestable faults in sequential circuits remains unsolved. Most of the previous works in untestability id...
Jaan Raik, Raimund Ubar, Anna Krivenko, Margus Kru...
117
Voted
VTS
2005
IEEE
84views Hardware» more  VTS 2005»
15 years 8 months ago
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
Ilia Polian, Sandip Kundu, Jean Marc Galliè...
106
Voted
DATE
2003
IEEE
87views Hardware» more  DATE 2003»
15 years 8 months ago
A Proposal for Transaction-Level Verification with Component Wrapper Language
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Koji Ara, Kei Suzuki
115
Voted
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
15 years 7 months ago
Symbolic exploration of large circuits with enhanced forward/backward traversals
Symbolic state space exploration techniques for Finite State Machines (FSMs) are a major recent result in CAD for VLSI. Most of them are exact and based on forward traversal, but ...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
124
Voted
ASPDAC
2001
ACM
112views Hardware» more  ASPDAC 2001»
15 years 6 months ago
Parameterized MAC unit implementation
Ethernet communication devices, such as adapter, hub, bridge and switch, all follow IEEE 802.3 standard protocol. We have designed and implemented an integrated 10/100 Mbps Etherne...
Ming-Chih Chen, Ing-Jer Huang, Chung-Ho Chen