1610 search results - page 66 / 322 » Testing Patterns |
118
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DELTA
2002
IEEE
15 years 7 months ago
2002
IEEE
: The way address sequences and data patterns appear on the outside of a memory may differ from their internal appearance; this effect is referred to as scrambling, which has a lar...
115
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DATE
2008
IEEE
15 years 8 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
124
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DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
Various X-filling methods have been proposed for reducing the shift and/or capture power in scan testing. The main drawback of these methods is that X-filling for low power leads t...
121
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ECCC
2010
15 years 2 months ago
2010
The rich collection of successes in property testing raises a natural question: Why are so many different properties turning out to be locally testable? Are there some broad "...
100
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DATE
2007
IEEE
15 years 8 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...