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IJOE
2007
107views more  IJOE 2007»
15 years 2 months ago
Learning Digital Test and Diagnostics via Internet
: An environment targeted to e-learning is presented for teaching design and test of electronic systems. The environment consists of a set of Java applets, and of web based access ...
Raimund Ubar, Artur Jutman, Margus Kruus, Elmet Or...
ITC
2003
IEEE
134views Hardware» more  ITC 2003»
15 years 7 months ago
Effectiveness Improvement of ECR Tests
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
Wanli Jiang, Erik Peterson, Bob Robotka
DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 6 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
15 years 7 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
DAC
2005
ACM
15 years 4 months ago
Path delay test compaction with process variation tolerance
In this paper we propose a test compaction method for path delay faults in a logic circuit. The method generates a compact set of two-pattern tests for faults on long paths select...
Seiji Kajihara, Masayasu Fukunaga, Xiaoqing Wen, T...