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DSD
2010
IEEE
144views Hardware» more  DSD 2010»
15 years 4 months ago
On-chip Scan-Based Test Strategy for a Dependable Many-Core Processor Using a NoC as a Test Access Mechanism
—Periodic on-chip scan-based tests have to be applied to a many-core processor SoC to improve its dependability. An infrastructural IP module has been designed and incorporated i...
Xiao Zhang, Hans G. Kerkhoff, Bart Vermeulen
DDECS
2007
IEEE
105views Hardware» more  DDECS 2007»
15 years 11 months ago
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
1-The increasing cost for System-on-Chip (SOC) testing is mainly due to the huge test data volumes that lead to long test application time and require large automatic test equipmen...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
117
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ACMSE
2006
ACM
15 years 10 months ago
Using genetic algorithms to generate test plans for functionality testing
Like in other fields, computer products (applications, hardware, etc.), before being marketed, require some level of testing to verify whether they meet their design and function...
Francisca Emanuelle Vieira, Francisco Martins, Raf...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 11 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
ISOLA
2004
Springer
15 years 10 months ago
Model Based Testing of Large-scale Software: How Can Simple Models Help to Test Complex System
The article is concerned with an approach to model based test development for large software systems. The approach presented is a part of UniTesK test development technology, which...
Victor V. Kuliamin