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VTS
2008
IEEE
77views Hardware» more  VTS 2008»
15 years 11 months ago
Test-Pattern Ordering for Wafer-Level Test-During-Burn-In
—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
Sudarshan Bahukudumbi, Krishnendu Chakrabarty
SAC
2009
ACM
15 years 11 months ago
Network protocol interoperability testing based on contextual signatures and passive testing
This paper presents a methodology for interoperability testing based on contextual signatures and passive testing with invariants. The concept of contextual signature offers a fra...
Fatiha Zaïdi, Emmanuel Bayse, Ana R. Cavalli
126
Voted
JSA
2000
103views more  JSA 2000»
15 years 4 months ago
Testing and built-in self-test - A survey
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
Andreas Steininger
VTS
2007
IEEE
89views Hardware» more  VTS 2007»
15 years 10 months ago
Test Set Reordering Using the Gate Exhaustive Test Metric
When a test set size is larger than desired, some patterns must be dropped. This paper presents a systematic method to reduce test set size; the method reorders a test set using t...
Kyoung Youn Cho, Edward J. McCluskey
129
Voted
DATE
2007
IEEE
106views Hardware» more  DATE 2007»
15 years 11 months ago
Optimized integration of test compression and sharing for SOC testing
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...