—Wafer-level test during burn-in (WLTBI) is a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, scan-based testing leads to significa...
This paper presents a methodology for interoperability testing based on contextual signatures and passive testing with invariants. The concept of contextual signature offers a fra...
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
When a test set size is larger than desired, some patterns must be dropped. This paper presents a systematic method to reduce test set size; the method reorders a test set using t...
1 The increasing test data volume needed to test core-based System-on-Chip contributes to long test application times (TAT) and huge automatic test equipment (ATE) memory requireme...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...