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VTS
2003
IEEE
122views Hardware» more  VTS 2003»
15 years 10 months ago
A Reconfigurable Shared Scan-in Architecture
In this paper, an efficient technique for test data volume reduction based on the shared scan-in (Illinois Scan) architecture and the scan chain reconfiguration (Dynamic Scan) arc...
Samitha Samaranayake, Emil Gizdarski, Nodari Sitch...
ITC
2003
IEEE
116views Hardware» more  ITC 2003»
15 years 10 months ago
BIST for Deep Submicron ASIC Memories with High Performance Application
Today’s ASIC designs consist of more memory in terms of both area and number of instances. The shrinking of geometries has an even greater effect upon memories due to their tigh...
Theo J. Powell, Wu-Tung Cheng, Joseph Rayhawk, Ome...
133
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VTS
2005
IEEE
106views Hardware» more  VTS 2005»
15 years 10 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...
ACSAC
2007
IEEE
15 years 11 months ago
Sania: Syntactic and Semantic Analysis for Automated Testing against SQL Injection
With the recent rapid increase in interactive web applications that employ back-end database services, an SQL injection attack has become one of the most serious security threats....
Yuji Kosuga, Kenji Kono, Miyuki Hanaoka, Miho Hish...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
16 years 5 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne