207 search results - page 18 / 42 » Testing and Model-Checking Techniques for Diagnosis |
DATE
2007
IEEE
15 years 6 months ago
2007
IEEE
Errors in timing closure process during the physical design stage may result in systematic silicon failures, such as scan chain hold time violations, which prohibit the test of ma...
DATE
2003
IEEE
15 years 5 months ago
2003
IEEE
The first non-enumerative framework for diagnosing path delay faults using zero suppressed binary decision diagrams is introduced. We show that fault free path delay faults with ...
KBSE
2007
IEEE
15 years 6 months ago
2007
IEEE
Concurrent programs are difficult to debug and verify because of the nondeterministic nature of concurrent executions. A particular concurrency-related bug may only show up under ...
DELTA
2008
IEEE
15 years 6 months ago
2008
IEEE
Scan is a widely used design-for-testability technique to improve test and diagnosis quality, however, scan chain failures account for almost 50% of chip failures. In this paper, ...
ECBS
2007
IEEE
15 years 6 months ago
2007
IEEE
Automated diagnosis of errors detected during software testing can improve the efficiency of the debugging process, and can thus help to make software more reliable. In this pape...