47 search results - page 7 / 10 » Testing and built-in self-test - A survey |
70
Voted
FPL
2004
Springer
15 years 2 months ago
2004
Springer
This paper presents a novel approach to interconnect fault location for FPGAs during power-on sequence. The method is based on a concept known as fault grading which utilizes defec...
84
Voted
ITC
1997
IEEE
15 years 1 months ago
1997
IEEE
Abstract- This paper describes a new method to generate analog signals with high precision at very low hardware complexity. This method consists in reproducing periodically a recor...
ISCAS
1999
IEEE
15 years 1 months ago
1999
IEEE
The main objectives of Built-In Self Test (BIST) are the design of test pattern generator circuits which achieve the highest fault coverage, require the shortest sequence of test ...
81
Voted
JSA
2000
14 years 9 months ago
2000
As the density of VLSI circuits increases it becomes attractive to integrate dedicated test logic on a chip. This Built-in Self-Test (BIST) approach not only offers economic benef...
DAC
2003
ACM
15 years 10 months ago
2003
ACM
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present...