Sciweavers

47 search results - page 8 / 10
» Testing and built-in self-test - A survey
Sort
View
86
Voted
DATE
2008
IEEE
226views Hardware» more  DATE 2008»
15 years 4 months ago
A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation
Abstract— We present a general method to evaluate RF BuiltIn Self-Test (BIST) techniques during the design stage. In particular, the adaptive kernel estimator is used to construc...
Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, ...
113
Voted
CSREAESA
2010
14 years 7 months ago
The First Clock Cycle Is A Real BIST
The primary goal of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) is to completely test all programmable logic and routing resources in the device such that ...
Charles E. Stroud, Bradley F. Dutton
80
Voted
ITC
2003
IEEE
149views Hardware» more  ITC 2003»
15 years 2 months ago
BIST for Xilinx 4000 and Spartan Series FPGAs: A Case Study
Abstract: We discuss the development of Built-In SelfTest (BIST) configurations that test all of the programmable logic and interconnect resources in the core of Xilinx 4000E, 4000...
Charles E. Stroud, Keshia N. Leach, Thomas A. Slau...
77
Voted
ITC
1997
IEEE
121views Hardware» more  ITC 1997»
15 years 1 months ago
BIST-Based Diagnostics of FPGA Logic Blocks
: Accurate diagnosis is an essential requirement in many testing environments, since it is the basis for any repair or replacement strategy used for chip or system fault-tolerance....
Charles E. Stroud, Eric Lee, Miron Abramovici
VLSID
2004
IEEE
135views VLSI» more  VLSID 2004»
15 years 10 months ago
Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique
Recent research for testable designs has focussed on inserting test structures by re-arranging an Register-TransferLevel (RTL) data path generated from a behavioural description t...
M. S. Gaur, Mark Zwolinski