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» Testing concurrent programs using value schedules
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DATE
1999
IEEE
147views Hardware» more  DATE 1999»
15 years 2 months ago
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
Nicola Nicolici, Bashir M. Al-Hashimi
CLUSTER
2001
IEEE
15 years 1 months ago
A Class of Loop Self-Scheduling for Heterogeneous Clusters
Distributed Computing Systems are a viable and less expensive alternative to parallel computers. However, a serious difficulty in concurrent programming of a distributed system is...
Anthony T. Chronopoulos, Manuel Benche, Daniel Gro...
VTS
2007
IEEE
95views Hardware» more  VTS 2007»
15 years 4 months ago
Delay Test Quality Evaluation Using Bounded Gate Delays
: Conventionally, path delay tests are derived in a delay-independent manner, which causes most faults to be robustly untestable. Many non-robust tests are found but, in practice, ...
Soumitra Bose, Vishwani D. Agrawal
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
15 years 3 months ago
Scheduling under resource constraints using dis-equations
Scheduling is an important step in high-level synthesis (HLS). In our tool, we perform scheduling in two steps: coarse-grain scheduling, in which we take into account the whole co...
Hadda Cherroun, Alain Darte, Paul Feautrier
ASPLOS
2009
ACM
15 years 10 months ago
CTrigger: exposing atomicity violation bugs from their hiding places
Multicore hardware is making concurrent programs pervasive. Unfortunately, concurrent programs are prone to bugs. Among different types of concurrency bugs, atomicity violation bu...
Soyeon Park, Shan Lu, Yuanyuan Zhou