6800 search results - page 282 / 1360 » Testing with Functions as Specifications |
175
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VLSID
2005
IEEE
15 years 12 months ago
2005
IEEE
During pseudorandom testing, a significant amount of energy and test application time is wasted for generating and for applying “useless” test vectors that do not contribute t...
189
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DATE
1999
IEEE
15 years 10 months ago
1999
IEEE
In this paper, new and efficient BIST methodology and BIST hardware insertion algorithms are presented for RTL data paths obtained from high level synthesis. The methodology is ba...
163
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VLSID
1993
IEEE
15 years 10 months ago
1993
IEEE
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
172
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IWANN
2009
Springer
16 years 25 days ago
2009
Springer
Generating test data for formal state based specifications is computationally expensive. This paper improves a framework that addresses this issue by representing the test data ge...
172
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DFT
2003
IEEE
15 years 11 months ago
2003
IEEE
Test scheduling and Test Access Mechanism (TAM) design are two important tasks in the development of a System-on-Chip (SOC) test solution. Previous test scheduling techniques assu...