6800 search results - page 285 / 1360 » Testing with Functions as Specifications |
170
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DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
188
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ETS
2006
IEEE
16 years 1 months ago
2006
IEEE
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
202
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ISSRE
2006
IEEE
16 years 28 days ago
2006
IEEE
—Graphical user interfaces (GUIs) are used as front ends to most of today’s software applications. The event-driven nature of GUIs presents new challenges for testing. One impo...
177
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VTS
1996
IEEE
15 years 11 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
156
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
This paper presents STEPS, an innovative softwarebased approach for testing P1500-compliant SoCs. STEPS is based on the concept that the ATE is not considered as an initiator appl...