In this paper, we propose a new approach for gated bus synthesis [16] with minimum wire capacitance per transaction in three-dimensional (3D) ICs. The 3D IC technology connects di...
Chung-Kuan Cheng, Peng Du, Andrew B. Kahng, Shih-H...
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
Multi-label learning arises in many real-world tasks where an object is naturally associated with multiple concepts. It is well-accepted that, in order to achieve a good performan...
The practice of software development can likely be improved if an externalized model of each programmer's knowledge of a particular code base is available. Some tools already...
As the amount of data being generated in biology has increased, a major challenge has been how to store and represent this data in a way that makes it easily accessible to researc...
Michael Backhaus, Janet Kelso, Joshua Bacher, Hein...