1728 search results - page 81 / 346 » The Accelerated Euclidean Algorithm |
107
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EURODAC
1990
IEEE
15 years 3 months ago
1990
IEEE
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
ARC
2008
Springer
15 years 1 months ago
2008
Springer
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
111
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GRAPHICSINTERFACE
2003
15 years 21 days ago
2003
We present a novel algorithm for simultaneous visual hull reconstruction and rendering by exploiting off-theshelf graphics hardware. The reconstruction is accomplished by projecti...
ICASSP
2011
IEEE
14 years 3 months ago
2011
IEEE
It is well known that LDPC decoding is computationally demanding and one of the hardest signal operations to parallelize. Beyond data dependencies that restrict the decoding of a ...
100
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FPGA
2012
ACM
13 years 7 months ago
2012
ACM
Memory bandwidth is critical to achieving high performance in many FPGA applications. The bandwidth of SDRAM memories is, however, highly dependent upon the order in which address...