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121
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EURODAC
1990
IEEE
92views VHDL» more  EURODAC 1990»
15 years 4 months ago
Accelerated test pattern generation by cone-oriented circuit partitioning
In this paper an efficient cone oriented circuit partitioning method is presented, which significantly speeds up automatic test pattern generation for combinational circuits. The ...
Torsten Grüning, Udo Mahlstedt, Wilfried Daeh...
102
Voted
ESOP
2010
Springer
15 years 4 months ago
CFA2: A Context-Free Approach to Control-Flow Analysis
Abstract. In a functional language, the dominant control-flow mechanism is function call and return. Most higher-order flow analyses, including k-CFA, do not handle call and retu...
Dimitrios Vardoulakis, Olin Shivers
82
Voted
CAEPIA
2007
Springer
15 years 4 months ago
Efficient Pruning of Operators in Planning Domains
Many recent successful planners use domain-independent heuristics to speed up the search for a valid plan. An orthogonal approach to accelerating search is to identify and remove r...
Anders Jonsson
ASPDAC
2004
ACM
113views Hardware» more  ASPDAC 2004»
15 years 4 months ago
Area-minimal algorithm for LUT-based FPGA technology mapping with duplication-free restriction
- Minimum area is one of the important objectives in technology mapping for lookup table-based FPGAs. It has been proven that the problem is NP-complete. This paper presents a poly...
Chi-Chou Kao, Yen-Tai Lai
115
Voted
CASES
2004
ACM
15 years 4 months ago
Scalable custom instructions identification for instruction-set extensible processors
Extensible processors allow addition of application-specific custom instructions to the core instruction set architecture. However, it is computationally expensive to automaticall...
Pan Yu, Tulika Mitra