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» The Bandwidth Exchange Architecture
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DATE
2007
IEEE
142views Hardware» more  DATE 2007»
15 years 8 months ago
Optimizing instruction-set extensible processors under data bandwidth constraints
We present a methodology for generating optimized architectures for data bandwidth constrained extensible processors. We describe a scalable Integer Linear Programming (ILP) formu...
Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Way...
DAC
2003
ACM
15 years 7 months ago
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
This paper describes a low-power design methodology for a bus architecture based on hybrid current/voltage mode signaling for deep sub-micrometer on-chip interconnects that achiev...
Rizwan Bashirullah, Wentai Liu, Ralph K. Cavin III
INFOCOM
2006
IEEE
15 years 8 months ago
Control Plane for Advance Bandwidth Scheduling in Ultra High-Speed Networks
— A control-plane architecture for supporting advance reservation of dedicated bandwidth channels on a switched network infrastructure is described including the front-end web in...
Nageswara S. V. Rao, Qishi Wu, Song Ding, Steven M...
ICNP
1999
IEEE
15 years 6 months ago
Evaluation of Bandwidth Broker Signaling
The Differentiated Services (DiffServ) architecture for the Internet implements a scalable mechanism for qualityof-service (QoS) provisioning. Bandwidth brokers represent the inst...
Manuel Günter, Torsten Braun
DAC
2012
ACM
13 years 4 months ago
A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC
Diverse IP cores are integrated on a modern system-on-chip and share resources. Off-chip memory bandwidth is often the scarcest resource and requires careful allocation. Two of t...
Min Kyu Jeong, Mattan Erez, Chander Sudanthi, Nige...