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» The Basics of Performance-Monitoring Hardware
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DATE
2010
IEEE
107views Hardware» more  DATE 2010»
15 years 2 months ago
An error-correcting unordered code and hardware support for robust asynchronous global communication
A new delay-insensitive data encoding scheme for global asynchronous communication is introduced. The goal of this work is to combine the timing-robustness of delay-insensitive (i....
Melinda Y. Agyekum, Steven M. Nowick
RECONFIG
2008
IEEE
225views VLSI» more  RECONFIG 2008»
15 years 4 months ago
A Hardware Filesystem Implementation for High-Speed Secondary Storage
Platform FPGAs are capable of hosting entire Linuxbased systems including standard peripherals, integrated network interface cards and even disk controllers on a single chip. File...
Ashwin A. Mendon, Ron Sass
EURODAC
1994
IEEE
209views VHDL» more  EURODAC 1994»
15 years 1 months ago
MOS VLSI circuit simulation by hardware accelerator using semi-natural models
- The accelerator is destined to circuit-level simulation of digital and analog/digital MOS VLSI'c containing of up to 100 thousand transistors (with 16 Mb RAM host-machine). ...
Victor V. Denisenko
ISMB
1994
14 years 11 months ago
High Speed Pattern Matching in Genetic Data Base with Reconfigurable Hardware
Homologydetection in large data bases is probably the most time consuming operation in molecular genetic computing systems. Moreover, the progresses made all around the world conc...
Eric Lemoine, Joël Quinqueton, Jean Sallantin
DAC
2008
ACM
14 years 11 months ago
SHIELD: a software hardware design methodology for security and reliability of MPSoCs
Security of MPSoCs is an emerging area of concern in embedded systems. Security is jeopardized by code injection attacks, which are the most common types of software attacks. Prev...
Krutartha Patel, Sri Parameswaran