632 search results - page 25 / 127 » The Basics of Performance-Monitoring Hardware |
ITC
2000
IEEE
15 years 2 months ago
2000
IEEE
—This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new register transfer (RT) level time redundancy-based concurrent error detection (CED)...
ISPASS
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Developing CPU scheduling algorithms and understanding their impact in practice can be difficult and time consuming due to the need to modify and test operating system ...
APCSAC
2007
IEEE
15 years 4 months ago
2007
IEEE
In this paper, a runtime performance projection model for dynamic power management is proposed. The model is built as a first-order linear equation using a linear regression model....
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
This paper presents sizing rules for basic building blocks in analog bipolar circuit design. Sizing rules efficiently capture design knowledge on the technology-specific level o...
67
Voted
DATE
1999
IEEE
15 years 2 months ago
1999
IEEE
In the reuse domain, the necessity of finding a new, more suitable description language opposes the need to make reuse an accepted practice, and thus related to standards. This pa...