632 search results - page 44 / 127 » The Basics of Performance-Monitoring Hardware |
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—We present the aEqualized routing algorithm: a novel algorithm for the Spidergon Network on Chip. AEqualized combines the well known aFirst and aLast algorithms proposed in lite...
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
DATE
2008
IEEE
15 years 4 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— This paper presents a new memory cell structure for content addressable memory (CAM) based on magnetic tunneling junction (MTJ). Each CAM cell employs a pair of differential MT...
ISCAS
2008
IEEE
15 years 4 months ago
2008
IEEE
— This paper presents ATLAS - a framework for automated analog circuit synthesis that comprises of both topology generation and subsequent circuit sizing. A hierarchically arrang...