Sciweavers

632 search results - page 50 / 127
» The Basics of Performance-Monitoring Hardware
Sort
View
MICRO
1996
IEEE
129views Hardware» more  MICRO 1996»
15 years 1 months ago
Trace Cache: A Low Latency Approach to High Bandwidth Instruction Fetching
As the issue widthof superscalar processors is increased, instructionfetch bandwidthrequirements will also increase. It will become necessary to fetch multiple basic blocks per cy...
Eric Rotenberg, Steve Bennett, James E. Smith
ISCAS
1994
IEEE
66views Hardware» more  ISCAS 1994»
15 years 1 months ago
High Speed FIR-Filter Architectures with Scalable Sample Rates
FIR ( nite impulse response) lters are widely used in digital signal processing. In this paper new architectures for high speed FIR lters with programmable coe cients are presente...
Martin Vaupel, Heinrich Meyr
MICRO
1994
IEEE
81views Hardware» more  MICRO 1994»
15 years 1 months ago
Register file port requirements of transport triggered architectures
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
Jan Hoogerbrugge, Henk Corporaal
ICCD
1992
IEEE
82views Hardware» more  ICCD 1992»
15 years 1 months ago
A Comparison of Self-Timed Design Using FPGA, CMOS, and GaAs Technologies
Asynchronous or self-timed systems that do not rely on a global clock to keep system components synchronized can offer significant advantages over traditional clocked circuits in ...
Erik Brunvand, Nick Michell, Kent F. Smith
ECBS
2006
IEEE
135views Hardware» more  ECBS 2006»
15 years 1 months ago
Model Checking Procedures for Infinite State Systems
The paper depicts experiments and results with preditraction based verification applied to infinite state Predicate abstraction is a method for automatic tion of abstract state sp...
Nikola Bogunovi, Edgar Pek