Sciweavers

632 search results - page 77 / 127
» The Basics of Performance-Monitoring Hardware
Sort
View
ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
15 years 4 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
SIGMETRICS
1999
ACM
15 years 4 months ago
NFS Sensitivity to High Performance Networks
This paper examines NFS sensitivity to performance characteristics of emerging networks. We adopt an unusual method of inserting controlled delays into live systems to measure sen...
Richard P. Martin, David E. Culler
ICCAD
1999
IEEE
108views Hardware» more  ICCAD 1999»
15 years 4 months ago
Copy detection for intellectual property protection of VLSI designs
We give the first study of copy detection techniques for VLSI CAD applications; these techniques are complementary to previous watermarking-based IP protection methods in finding ...
Andrew B. Kahng, Darko Kirovski, Stefanus Mantik, ...
ICCD
1999
IEEE
93views Hardware» more  ICCD 1999»
15 years 4 months ago
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
If a system-on-a-chip (SOC) contains an embedded processor, this paper presents a novel approach for using the processor to aid in testing the other components of the SOC. The bas...
Abhijit Jas, Nur A. Touba
MICRO
1999
IEEE
110views Hardware» more  MICRO 1999»
15 years 4 months ago
Balance Scheduling: Weighting Branch Tradeoffs in Superblocks
Since there is generally insufficient instruction level parallelism within a single basic block, higher performance is achieved by speculatively scheduling operations in superbloc...
Alexandre E. Eichenberger, Waleed Meleis